A Separator-Based Framework for Automated Partitioning and Mapping of Parallel Algorithms for Numerical Solution of PDEs

نویسندگان

  • Eric J. Schwabe
  • Guy E. Blelloch
  • Anja Feldmann
  • Omar Ghattas
  • John R. Gilbert
  • Gary L. Miller
  • David R. O'Hallaron
  • Jonathan R. Shewchuk
  • Shang-Hua Teng
چکیده

This paper is a report on ongoing work in developing automated systems for the partitioning, placement, and routing of data that is necessary for the e cient parallel solution of large problems in scienti c computing, speci cally the numerical solution of partial di erential equations. Many of these problems have as an iterated inner loop the formation of the product of a large sparse matrix and a vector of variables. This problem of sparse matrixvector multiplication has an underlying combinatorial graph structure that can be exploited. Using geometric information from the original problem, we can partition this combinatorial graph using provably good twoor three-dimensional graph sepThis research was supported in part by the Defense Advanced Research Projects Agency (DOD) monitored by DARPA/CMO under Contract MDA972{90{C{0035, the Air Force O ce of Scienti c Research under Contract F49620{92{J{0131, the Natural Sciences and Engineering Research Council of Canada under a 1967 Science and Engineering Scholarship, and the National Science Foundation under Grants CCR{8713489, CCR{9016641, DDM-9009597, and DDM-9114678. arators (depending on the dimension of the problem). The resulting partitions into subproblems have good load balancing properties and a relatively small amount of communication between subproblems. In order to develop e ective heuristics for the placement of these subproblems on the available processors and the routing of messages between them, we must also carefully consider the characteristics of the target architectures. The rst parallel machine we are considering is the iWarp system. The novel communication mechanism of the iWarp system allows us to draw an analogy between our placement and routing problem and certain area minimization problems in the eld of VLSI circuit layout, giving us an additional collection of insights and heuristics which can be brought to bear on our problem.

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تاریخ انتشار 1992